/**@file
 GPIO data for use with GPIO ASL lib

  Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
  SPDX-License-Identifier: BSD-2-Clause-Patent

**/

#include "Register/GpioV2MtlPchSRegs.h"
#include "GpioAcpiDefinesMtlPchS.h"

//
// If in GPIO_GROUP_INFO structure certain register doesn't exist
// it will have value equal to NO_REGISTER_FOR_PROPERTY
//
#define NO_REGISTER_FOR_PROPERTY 0xFFFF

//
// If in GPIO_GROUP_INFO structure certain group should not be used
// by GPIO OS driver then "Gpio base number" field should be set to below value
//
#define GPIO_OS_DRV_NOT_SUPPORTED 0xFFFF

Name (GPCS , Package() {
  Package() { // COM0
    MTL_PCH_GPIO_COM0,
    Package() {
      Package() { // GPP_D
        GPIOV2_MTL_PCH_S_GPP_D_PAD_MAX,
        R_GPIOV2_MTL_PCH_S_PCR_GPP_D_PAD_CFG_DW0,
        R_GPIOV2_MTL_PCH_S_PCR_GPP_D_HOSTSW_OWN,
        R_GPIOV2_MTL_PCH_S_PCR_GPP_D_PAD_OWN,
        R_GPIOV2_MTL_PCH_S_PCR_GPP_D_GPI_GPE_STS,
        R_GPIOV2_MTL_PCH_S_PCR_GPP_D_PADCFGLOCK,
        R_GPIOV2_MTL_PCH_S_PCR_GPP_D_PADCFGLOCKTX,
        GPIOV2_MTL_PCH_S_DRIVER_GPP_D_0,
        0
      },
      Package() { // GPP_R
        GPIOV2_MTL_PCH_S_GPP_R_PAD_MAX,
        R_GPIOV2_MTL_PCH_S_PCR_GPP_R_PAD_CFG_DW0,
        R_GPIOV2_MTL_PCH_S_PCR_GPP_R_HOSTSW_OWN,
        R_GPIOV2_MTL_PCH_S_PCR_GPP_R_PAD_OWN,
        R_GPIOV2_MTL_PCH_S_PCR_GPP_R_GPI_GPE_STS,
        R_GPIOV2_MTL_PCH_S_PCR_GPP_R_PADCFGLOCK,
        R_GPIOV2_MTL_PCH_S_PCR_GPP_R_PADCFGLOCKTX,
        GPIOV2_MTL_PCH_S_DRIVER_GPP_R_0,
        1
      },
      Package() { // GPP_J
        GPIOV2_MTL_PCH_S_GPP_J_PAD_MAX,
        R_GPIOV2_MTL_PCH_S_PCR_GPP_J_PAD_CFG_DW0,
        R_GPIOV2_MTL_PCH_S_PCR_GPP_J_HOSTSW_OWN,
        R_GPIOV2_MTL_PCH_S_PCR_GPP_J_PAD_OWN,
        R_GPIOV2_MTL_PCH_S_PCR_GPP_J_GPI_GPE_STS,
        R_GPIOV2_MTL_PCH_S_PCR_GPP_J_PADCFGLOCK,
        R_GPIOV2_MTL_PCH_S_PCR_GPP_J_PADCFGLOCKTX,
        GPIOV2_MTL_PCH_S_DRIVER_GPP_J_0,
        2
      },
      Package() { // VGPIO
        GPIOV2_MTL_PCH_S_VGPIO_PAD_MAX,
        R_GPIOV2_MTL_PCH_S_PCR_VGPIO_PAD_CFG_DW0,
        R_GPIOV2_MTL_PCH_S_PCR_VGPIO_HOSTSW_OWN,
        R_GPIOV2_MTL_PCH_S_PCR_VGPIO_PAD_OWN,
        R_GPIOV2_MTL_PCH_S_PCR_VGPIO_GPI_GPE_STS,
        R_GPIOV2_MTL_PCH_S_PCR_VGPIO_PADCFGLOCK,
        R_GPIOV2_MTL_PCH_S_PCR_VGPIO_PADCFGLOCKTX,
        GPIOV2_MTL_PCH_S_DRIVER_VGPIO_0,
        3
      }
    }
  },
  Package() { // COM1
    MTL_PCH_GPIO_COM1,
    Package() {
      Package() { // GPP_A
        GPIOV2_MTL_PCH_S_GPP_A_PAD_MAX,
        R_GPIOV2_MTL_PCH_S_PCR_GPP_A_PAD_CFG_DW0,
        R_GPIOV2_MTL_PCH_S_PCR_GPP_A_HOSTSW_OWN,
        R_GPIOV2_MTL_PCH_S_PCR_GPP_A_PAD_OWN,
        R_GPIOV2_MTL_PCH_S_PCR_GPP_A_GPI_GPE_STS,
        R_GPIOV2_MTL_PCH_S_PCR_GPP_A_PADCFGLOCK,
        R_GPIOV2_MTL_PCH_S_PCR_GPP_A_PADCFGLOCKTX,
        GPIOV2_MTL_PCH_S_DRIVER_GPP_A_0,
        4
      },
      Package() { // DIR_ESPI
        GPIOV2_MTL_PCH_S_DIR_ESPI_PAD_MAX,
        R_GPIOV2_MTL_PCH_S_PCR_DIR_ESPI_PAD_CFG_DW0,
        R_GPIOV2_MTL_PCH_S_PCR_DIR_ESPI_HOSTSW_OWN,
        R_GPIOV2_MTL_PCH_S_PCR_DIR_ESPI_PAD_OWN,
        R_GPIOV2_MTL_PCH_S_PCR_DIR_ESPI_GPI_GPE_STS,
        R_GPIOV2_MTL_PCH_S_PCR_DIR_ESPI_PADCFGLOCK,
        R_GPIOV2_MTL_PCH_S_PCR_DIR_ESPI_PADCFGLOCKTX,
        GPIOV2_MTL_PCH_S_DRIVER_PWRBTNB_OUT,
        5
      },
      Package() { // GPP_B
        GPIOV2_MTL_PCH_S_GPP_B_PAD_MAX,
        R_GPIOV2_MTL_PCH_S_PCR_GPP_B_PAD_CFG_DW0,
        R_GPIOV2_MTL_PCH_S_PCR_GPP_B_HOSTSW_OWN,
        R_GPIOV2_MTL_PCH_S_PCR_GPP_B_PAD_OWN,
        R_GPIOV2_MTL_PCH_S_PCR_GPP_B_GPI_GPE_STS,
        R_GPIOV2_MTL_PCH_S_PCR_GPP_B_PADCFGLOCK,
        R_GPIOV2_MTL_PCH_S_PCR_GPP_B_PADCFGLOCKTX,
        GPIOV2_MTL_PCH_S_DRIVER_GPP_B_0,
        6
      }
    }
  },
  Package() { // COM2
    MTL_PCH_GPIO_COM2,
    Package() {
      Package() { // DSW
        GPIOV2_MTL_PCH_S_DSW_PAD_MAX,
        R_GPIOV2_MTL_PCH_S_PCR_DSW_PAD_CFG_DW0,
        R_GPIOV2_MTL_PCH_S_PCR_DSW_HOSTSW_OWN,
        R_GPIOV2_MTL_PCH_S_PCR_DSW_PAD_OWN,
        R_GPIOV2_MTL_PCH_S_PCR_DSW_GPI_GPE_STS,
        R_GPIOV2_MTL_PCH_S_PCR_DSW_PADCFGLOCK,
        R_GPIOV2_MTL_PCH_S_PCR_DSW_PADCFGLOCKTX,
        GPIO_OS_DRV_NOT_SUPPORTED,
        GPIO_OS_DRV_NOT_SUPPORTED
      }
    }
  },
  Package() { // COM3
    MTL_PCH_GPIO_COM3,
    Package() {
      Package() { // SPI0
        GPIOV2_MTL_PCH_S_SPI0_PAD_MAX,
        R_GPIOV2_MTL_PCH_S_PCR_SPI0_PAD_CFG_DW0,
        R_GPIOV2_MTL_PCH_S_PCR_SPI0_HOSTSW_OWN,
        R_GPIOV2_MTL_PCH_S_PCR_SPI0_PAD_OWN,
        R_GPIOV2_MTL_PCH_S_PCR_SPI0_GPI_GPE_STS,
        R_GPIOV2_MTL_PCH_S_PCR_SPI0_PADCFGLOCK,
        R_GPIOV2_MTL_PCH_S_PCR_SPI0_PADCFGLOCKTX,
        GPIOV2_MTL_PCH_S_DRIVER_SPI0_IO_2,
        8
      },
      Package() { // GPP_C
        GPIOV2_MTL_PCH_S_GPP_C_PAD_MAX,
        R_GPIOV2_MTL_PCH_S_PCR_GPP_C_PAD_CFG_DW0,
        R_GPIOV2_MTL_PCH_S_PCR_GPP_C_HOSTSW_OWN,
        R_GPIOV2_MTL_PCH_S_PCR_GPP_C_PAD_OWN,
        R_GPIOV2_MTL_PCH_S_PCR_GPP_C_GPI_GPE_STS,
        R_GPIOV2_MTL_PCH_S_PCR_GPP_C_PADCFGLOCK,
        R_GPIOV2_MTL_PCH_S_PCR_GPP_C_PADCFGLOCKTX,
        GPIOV2_MTL_PCH_S_DRIVER_GPP_C_0,
        9
      },
      Package() { // GPP_H
        GPIOV2_MTL_PCH_S_GPP_H_PAD_MAX,
        R_GPIOV2_MTL_PCH_S_PCR_GPP_H_PAD_CFG_DW0,
        R_GPIOV2_MTL_PCH_S_PCR_GPP_H_HOSTSW_OWN,
        R_GPIOV2_MTL_PCH_S_PCR_GPP_H_PAD_OWN,
        R_GPIOV2_MTL_PCH_S_PCR_GPP_H_GPI_GPE_STS,
        R_GPIOV2_MTL_PCH_S_PCR_GPP_H_PADCFGLOCK,
        R_GPIOV2_MTL_PCH_S_PCR_GPP_H_PADCFGLOCKTX,
        GPIOV2_MTL_PCH_S_DRIVER_GPP_H_0,
        10
      },
      Package() { // VGPIO3
        GPIOV2_MTL_PCH_S_VGPIO_3_PAD_MAX,
        R_GPIOV2_MTL_PCH_S_PCR_VGPIO_3_PAD_CFG_DW0,
        R_GPIOV2_MTL_PCH_S_PCR_VGPIO_3_HOSTSW_OWN,
        R_GPIOV2_MTL_PCH_S_PCR_VGPIO_3_PAD_OWN,
        R_GPIOV2_MTL_PCH_S_PCR_VGPIO_3_GPI_GPE_STS,
        R_GPIOV2_MTL_PCH_S_PCR_VGPIO_3_PADCFGLOCK,
        R_GPIOV2_MTL_PCH_S_PCR_VGPIO_3_PADCFGLOCKTX,
        GPIOV2_MTL_PCH_S_DRIVER_VGPIO_PCIE_80,
        11
      },
      Package() { // VGPIO0
        GPIOV2_MTL_PCH_S_VGPIO_0_PAD_MAX,
        R_GPIOV2_MTL_PCH_S_PCR_VGPIO_0_PAD_CFG_DW0,
        R_GPIOV2_MTL_PCH_S_PCR_VGPIO_0_HOSTSW_OWN,
        R_GPIOV2_MTL_PCH_S_PCR_VGPIO_0_PAD_OWN,
        R_GPIOV2_MTL_PCH_S_PCR_VGPIO_0_GPI_GPE_STS,
        R_GPIOV2_MTL_PCH_S_PCR_VGPIO_0_PADCFGLOCK,
        R_GPIOV2_MTL_PCH_S_PCR_VGPIO_0_PADCFGLOCKTX,
        GPIOV2_MTL_PCH_S_DRIVER_VGPIO_USB_0,
        12
      },
      Package() { // VGPIO4
        GPIOV2_MTL_PCH_S_VGPIO_4_PAD_MAX,
        R_GPIOV2_MTL_PCH_S_PCR_VGPIO_4_PAD_CFG_DW0,
        R_GPIOV2_MTL_PCH_S_PCR_VGPIO_4_HOSTSW_OWN,
        R_GPIOV2_MTL_PCH_S_PCR_VGPIO_4_PAD_OWN,
        R_GPIOV2_MTL_PCH_S_PCR_VGPIO_4_GPI_GPE_STS,
        R_GPIOV2_MTL_PCH_S_PCR_VGPIO_4_PADCFGLOCK,
        R_GPIOV2_MTL_PCH_S_PCR_VGPIO_4_PADCFGLOCKTX,
        GPIOV2_MTL_PCH_S_DRIVER_VGPIO_ISCLK_0,
        13
      }
    }
  },
  Package() { // COM4
    MTL_PCH_GPIO_COM4,
    Package() {
      Package() { // GPP_S
        GPIOV2_MTL_PCH_S_GPP_S_PAD_MAX,
        R_GPIOV2_MTL_PCH_S_PCR_GPP_S_PAD_CFG_DW0,
        R_GPIOV2_MTL_PCH_S_PCR_GPP_S_HOSTSW_OWN,
        R_GPIOV2_MTL_PCH_S_PCR_GPP_S_PAD_OWN,
        R_GPIOV2_MTL_PCH_S_PCR_GPP_S_GPI_GPE_STS,
        R_GPIOV2_MTL_PCH_S_PCR_GPP_S_PADCFGLOCK,
        R_GPIOV2_MTL_PCH_S_PCR_GPP_S_PADCFGLOCKTX,
        GPIOV2_MTL_PCH_S_DRIVER_GPP_S_0,
        14
      },
      Package() { // GPP_E
        GPIOV2_MTL_PCH_S_GPP_E_PAD_MAX,
        R_GPIOV2_MTL_PCH_S_PCR_GPP_E_PAD_CFG_DW0,
        R_GPIOV2_MTL_PCH_S_PCR_GPP_E_HOSTSW_OWN,
        R_GPIOV2_MTL_PCH_S_PCR_GPP_E_PAD_OWN,
        R_GPIOV2_MTL_PCH_S_PCR_GPP_E_GPI_GPE_STS,
        R_GPIOV2_MTL_PCH_S_PCR_GPP_E_PADCFGLOCK,
        R_GPIOV2_MTL_PCH_S_PCR_GPP_E_PADCFGLOCKTX,
        GPIOV2_MTL_PCH_S_DRIVER_GPP_E_0,
        15
      },
      Package() { // GPP_K
        GPIOV2_MTL_PCH_S_GPP_K_PAD_MAX,
        R_GPIOV2_MTL_PCH_S_PCR_GPP_K_PAD_CFG_DW0,
        R_GPIOV2_MTL_PCH_S_PCR_GPP_K_HOSTSW_OWN,
        R_GPIOV2_MTL_PCH_S_PCR_GPP_K_PAD_OWN,
        R_GPIOV2_MTL_PCH_S_PCR_GPP_K_GPI_GPE_STS,
        R_GPIOV2_MTL_PCH_S_PCR_GPP_K_PADCFGLOCK,
        R_GPIOV2_MTL_PCH_S_PCR_GPP_K_PADCFGLOCKTX,
        GPIOV2_MTL_PCH_S_DRIVER_GPP_K_0,
        16
      },
      Package() { // GPP_F
        GPIOV2_MTL_PCH_S_GPP_F_PAD_MAX,
        R_GPIOV2_MTL_PCH_S_PCR_GPP_F_PAD_CFG_DW0,
        R_GPIOV2_MTL_PCH_S_PCR_GPP_F_HOSTSW_OWN,
        R_GPIOV2_MTL_PCH_S_PCR_GPP_F_PAD_OWN,
        R_GPIOV2_MTL_PCH_S_PCR_GPP_F_GPI_GPE_STS,
        R_GPIOV2_MTL_PCH_S_PCR_GPP_F_PADCFGLOCK,
        R_GPIOV2_MTL_PCH_S_PCR_GPP_F_PADCFGLOCKTX,
        GPIOV2_MTL_PCH_S_DRIVER_GPP_F_0,
        17
      }
    }
  },
  Package() { // COM5
    MTL_PCH_GPIO_COM5,
    Package() {
      Package() { // GPP_I
        GPIOV2_MTL_PCH_S_GPP_I_PAD_MAX,
        R_GPIOV2_MTL_PCH_S_PCR_GPP_I_PAD_CFG_DW0,
        R_GPIOV2_MTL_PCH_S_PCR_GPP_I_HOSTSW_OWN,
        R_GPIOV2_MTL_PCH_S_PCR_GPP_I_PAD_OWN,
        R_GPIOV2_MTL_PCH_S_PCR_GPP_I_GPI_GPE_STS,
        R_GPIOV2_MTL_PCH_S_PCR_GPP_I_PADCFGLOCK,
        R_GPIOV2_MTL_PCH_S_PCR_GPP_I_PADCFGLOCKTX,
        GPIOV2_MTL_PCH_S_DRIVER_GPP_I_0,
        18
      },
      Package() { // JTAG_CPU
        GPIOV2_MTL_PCH_S_JTAG_CPU_PAD_MAX,
        R_GPIOV2_MTL_PCH_S_PCR_JTAG_CPU_PAD_CFG_DW0,
        R_GPIOV2_MTL_PCH_S_PCR_JTAG_CPU_HOSTSW_OWN,
        R_GPIOV2_MTL_PCH_S_PCR_JTAG_CPU_PAD_OWN,
        R_GPIOV2_MTL_PCH_S_PCR_JTAG_CPU_GPI_GPE_STS,
        R_GPIOV2_MTL_PCH_S_PCR_JTAG_CPU_PADCFGLOCK,
        R_GPIOV2_MTL_PCH_S_PCR_JTAG_CPU_PADCFGLOCKTX,
        GPIOV2_MTL_PCH_S_DRIVER_JTAG_TDO,
        19
      }
    }
  }
})